This invention relates to electronic circuits and, more particularly the design and validation of electronic circuits.
In order to fabricate an electronic circuit such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), a number of steps must be performed. The first step is to design the circuit at a xe2x80x9cbehavioralxe2x80x9d level. The behavioral level is the top level of the design hierarchy. Additional steps are performed on the behavioral level to define a hardware level that characterizes the circuit using actual hardware components. The hardware level is the lowest level of the design hierarchy.
The behavioral level description typically includes a block diagram or netlist that describes the various functions of the circuit in relatively general terms. The hardware level is based on the behavioral level description. The behavioral level description does not have enough specificity to fully enable a circuit manufacturer to implement the circuit design. The conventional approach is to manually generate an electronic file that characterizes the circuit at the hardware level in a programming language such as hardware description language (HDL). A design engineer goes through the behavioral description on a component-by-component basis and generates the necessary code sets in the programming language. This approach is labor intensive and subject to human error.
Once the electronic file has been manually generated, a complex verification process is required. In the case of the ASIC design, the functionality is extensively verified from a model of the circuit written in C-code. A select set of C-code input simulation vectors (i.e. input sequences) are then also applied to the HDL circuit model. In this co-simulation, the output vectors from the HDL model are compared bit by bit to the corresponding output vectors from the C-code model to establish a correspondence between the performance verified by the C-code model and the hardware actually being fabricated. This is typically required due to the complexity of the ASIC chip and the difficulty in performing a functional simulation in HDL, the complexity and cost of the ASIC fabrication process, and the need for a high level of certainty as to the functionality and first pass success of the electronic file and its subsequent fabrication.
The manual generation of the C-code model also requires detailed knowledge of C-code which increases the labor costs that are associated with design and fabrication. Once the electronic file has been verified, it is typically converted to the format used by the manufacturer with a conversion program such as Synopsis. After the electronic file has been converted, the manufacturer fabricates the circuit.
In U.S. Pat. No. 6,077,303 to Mandell et al. and U.S. Pat. No. 6,477,689 to Mandell et al., a design tool and method for simplifying the design of electronic circuits such as ASICs is disclosed. The design tool and method generates symbolic and numeric equations. In Mandell et al. ""303, a method is disclosed for verifying that a system that is built from smaller components implements a desired equation that represents the system. Symbolic data is clocked through the system by processing a symbolic test vector using linked equations that are written for each component of the system. The resulting symbolic equation, generated at the output of the system, is stored. The symbolic equation is then compared with the desired equation for the system using a symbolic manipulation tool. If the comparison generates a zero difference, the system correctly implements the desired equation that correctly represents the system.
A design tool and method according to the invention for characterizing a circuit at a hardware level includes the steps of creating a behavioral level description of the circuit and generating a netlist from the behavioral level description. Reference equations are generated from the netlist. The reference equations are translated into numeric and symbolic C-code. The symbolic C-code is compared to the numeric C-code for validation.
In other features of the invention, the reference equations are translated into numeric and symbolic HDL-code. The symbolic HDL-code is compared to the numeric HDL-code for validation. The symbolic C-code is compiled and simulated. A C-code equation file is generated. The symbolic HDL-code is compiled and simulated. A HDL-code equation file is generated. A symbolic manipulation program is used to solve for a difference between the C-code equation file and the HDL-code equation file. If there are no unexpected differences, equivalence is established.
It is to be understood that both the foregoing general description and the following detailed description are merely exemplary of the invention, and are intended to provide an overview or framework for understanding the nature and character of the invention as it is claimed. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute part of this specification. The drawings illustrate various features and embodiments of the invention, and together with the description serve to explain the principles and operation of the invention.